Inspire, develop and lead a team of engineering/production staff to deliver software test suites to validate complex assembly of MI300 products in MFGLeverage extensive experience in IC Design, Validation to influence Roadmap and T[...]
Provide end-to-end ownership of the quality, coverage, and completeness of Diagnostics solution to multiple programs.Highlights project goals, strategies, risks, and key requirements of Diagnostics, tools, and framework to help PMs, Ma[...]
As a member of the GPU Technologies and Engineering (G&E) group, you will help bring to life cutting-edge designs. As a member of the Physical Design team, you will work closely with the architecture, IP design, front-end design/inte[...]
Lead I&C System design and development from conceptual through preliminary and detailed design, fabrication, assembly, production test, validation test as well as site installation, start-up test, and commissioning.Perform, lead, or ma[...]
As a full stack architect, you will lead the architecture of cloud native applications and infrastructures to drive the creation industry leading products. You will define practical architectures that ensure the performance, scalabilit[...]
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AMD together we advance_ THE ROLE: As a member of the GPU Technologies and Engineering (G&E) group, you will help bring to life cutting-edge designs. As a member of the Physical Design team, you will work closely with the architectur[...]
AMD together we advance_ DESIGN VERIFICATION ENGINEER THE ROLE: As a member of the GPU Technologies and Engineering group, you will help bring to life cutting-edge designs. As a member of the front-end design/verification team, you w[...]
As a DC GPU Manufacturing Validation and Test Automation Engineer, you will work with a cross-functional organization to plan, develop, and validate test content and automation for AMD’s manufacturing test program.   Responsibiliti[...]
Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructureDevelop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed te[...]