AMD together we advance_ DESIGN VERIFICATION ENGINEER THE ROLE: As a member of the GPU Technologies and Engineering group, you will help bring to life cutting-edge designs. As a member of the front-end design/verification team, you w[...]
As a DC GPU Manufacturing Validation and Test Automation Engineer, you will work with a cross-functional organization to plan, develop, and validate test content and automation for AMD’s manufacturing test program.   Responsibiliti[...]
Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructureDevelop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed te[...]
You'll actively establish, maintain, and strengthen internal and external relationships. You'll identify potential business opportunities for EY. You will develop long-term client relationships and networks. You'll provide innovative c[...]
Verification of critical high speed digital designs using both coverage driven random and directed testing techniques.Work on various aspects of the Verification flow from initial test planning to coverage convergence and sign-off clos[...]
Purpose defines who we are and gives us reason to exist as an organization. Enjoy flexible, proactive, and practical benefits that foster a culture of well-being and connectedness. Experience a firm where wellness matters. Be expected [...]
We are looking for a talented eLearning Instructional Designer who thrives in a creative and collaborative environment. You will be responsible for working with Stakeholders and SME’s to design and develop eLearning Courseware for th[...]
​​ Position Title: Learning Experience Designer Position Type: Regular - Full-Time ​ Position Location: Toronto HQ Grade: Grade 05 Requisition ID: 27902 ​ For us, for family! We know the importance that food plays in people's l[...]
Excellent knowledge of C, C++, SystemVerilog, UVM object-oriented design as well as scripting language.Experience in ground up development and verification using UVM/SystemVerilog with IP and Subsystem verification as main objective us[...]